In a general dynamic random access memory (DRAM), a memory cell includes one transistor (1T) and one capacitor (1C). Such a 1T1C DRAM is a memory capable of retaining data by accumulating electric charge in a capacitor and thus has no limit on endurance in principle. As a high-capacity memory device, the DRAM is incorporated into a number of electronic devices because of writing and reading at high speed and a small number of elements in memory cells, which facilitates high integration. The 1T1C DRAM performs data reading in such a manner that electric charge accumulated in the capacitor is released to a bit line and a potential change of the bit line is measured; therefore, the capacitance of the capacitor needs to be kept at a certain value or more. As a result, miniaturization of the memory cell makes it more and more difficult to keep required capacitance.
A gain cell including two or three transistors has been proposed (e.g., Patent Documents 1 and 2). In the gain cell, the amount of accumulated electric charge can be amplified by a read transistor and the amplified electric charge can be supplied to a bit line; therefore, it is possible to reduce the capacitance of a capacitor.
A transistor including a metal oxide in a channel formation region (hereinafter such a transistor is referred to as a metal oxide semiconductor transistor or an OS transistor in some cases) is known. For example, a storage device in which a write transistor of a gain cell is an OS transistor has been disclosed in each of Patent Document 3 and Non-Patent Document 1.
In this specification and the like, a memory including an OS transistor in a memory cell, as described in Patent Document 3, is referred to as an OS memory. As in Non-Patent Document 1, a gain-cell DRAM in which a write transistor is an OS transistor is referred to as “NOSRAM” (registered trademark). “NOSRAM” stands for nonvolatile oxide semiconductor RAM.